1. Field of the Invention
The invention relates to an interface for an integrated circuit and particularly to a control interface that can allow variable length input data streams, provide a buffering function, and facilitate monitoring of both digital and analog signals.
2. Description of the Related Art
The functionality and monitoring of an integrated circuit can be significantly limited by the number of pins on the integrated circuit. In fact, this problem has forced some systems to resort to providing discrete integrated circuits for various critical functions. These discrete integrated circuits increase the system""s ability to monitor such functions, but undesirably increase both the size and cost of the system.
Thus, integrated circuits have continued to integrate additional functionality without having a commensurate capability to monitor such additional functionality. To solve this problem, some integrated circuits include control circuitry in a limited, predetermined area of the chip and use thousands of lines to detect conditions in or provide signals to other areas of the chip. However, these lines can create significant challenges in routing and undesirably increase the size of the integrated circuit.
In a purely digital device, controllability and observability can be provided using the 1999 IEEE 1149.1 standard, also called boundary-scan, which was promulgated by the the Joint Test Action Group (JTAG). This standard defines a set of design rules that allow virtual access to nodes in an integrated circuit during its debugging and production test. However, boundary scan is not adequate for highly integrated systems that include analog and/or mixed signal (i.e. both analog and digital) integrated circuits. Moreover, during the normal operation mode, boundary-scan is inactive and thus cannot facilitate monitoring or changing the functionality of the integrated circuit.
Some integrated circuits include large shift registers to change their functionality, wherein new configurations for the integrated circuits can be theoretically loaded when needed. However, many systems cannot interrupt normal operation for the time needed to load these large shift registers. Thus, in these systems, configuration of such integrated circuits is typically limited to a power up operation.
Therefore, a need arises for a system and method of monitoring highly integrated circuits as well as allowing the re-configuration of such integrated circuits.
In accordance with one feature of the invention, a control interface of an integrated circuit can provide buffering of input data packets, thereby allowing configurations of the integrated circuit to be modified quickly and efficiently. Moreover, the control interface can be sized and configured to monitor digital signals from any number of nodes on an integrated circuit, thereby facilitating the testing, lab characterization, and debugging of those nodes. Finally, the control interface can advatageously control the monitoring of analog components on the integrated circuit, thereby significantly reducing the number of pins for such monitoring. The control interface has particular relevance to highly integrated circuits, such as radio transceivers, which can have extremely demanding requirements when interfacing to other integrated circuits, e.g. broadband devices.
The control interface includes a plurality of buffer registers for receiving the input data packet. The control interface further includes a plurality of control registers, wherein each control register can be loaded from its associated buffer register. The control registers are coupled in operative relation to functional blocks on the integrated circuit. These functional blocks can perform various functions, which can utilize analog and/or mixed (i.e. a combination of analog and digital) signals. In one embodiment, the plurality of buffer registers are coupled to input pins of the integrated circuit.
In accordance with one feature of the invention, the buffer registers can have different lengths. However, a control register has the same length as its associated buffer register. Thus, a buffer/control register can be characterized as a xe2x80x9clongxe2x80x9d or xe2x80x9cshortxe2x80x9d register. A short register can include N or less flip-flops and a long register includes more than N flip-flops. In one embodiment, N is approximately 6.
In one embodiment, the integrated circuit can implement a radio transceiver. In this embodiment, the short buffer registers can be used to load dynamically adjustable control values and the long buffer registers can be used to load static configuration control values.
The integrated circuit can further include an analog line coupled to a pin of the integrated circuit. Multiple analog components on the integrated circuit can be selectively coupled to the analog line using corresponding digital switches. The control interface can advantageously configure and/or set one or more function blocks to control these switches. In this manner, the control interface minimizes the number of pins necessary to access parameters associated with each analog component.
The control interface can further include a multiplexer that receives signals provided by the plurality of buffer registers and the plurality of control registers. The multiplexer can also receive one or more user data signals on the integrated circuit. Therefore, the control interface advantageously allows access to many digital nodes in the integrated circuit, thereby facilitating the testing, lab characterization, and debugging of those nodes. In one embodiment, the multiplexer is coupled to an output pin of the integrated circuit.
A method of providing an interface on an integrated circuit is described. The method includes buffering a data packet received by pins on the integrated circuit. The buffering can be performed by a plurality of buffer register sets. The data packet can be selectively transferred from one of buffer register sets into a designated control register set. The designated control register set can configure and/or control a functional block on the integrated circuit. Because the data packet is buffered, these values can be transferred without interrupting operation of the functional block. The control interface can also allow access to content stored by each buffer and control register, thereby facilitating testing and calibration of many nodes in the integrated circuit.
In accordance with one feature of the invention, the buffer registers can have different lengths. The buffer registers can be organized into buffer register sets (with corresponding control register sets). The buffer register sets receive the same data packet. However, each buffer register in the set receives a different data stream, wherein all the data streams form the data packet. In one embodiment, the buffer registers can receive data streams of different lengths. If the length of a buffer register is shorter than its received data stream, then a data overflow condition occurs.
In accordance with another feature of the invention, an address is appended to the end of one of the data streams. The control interface can include an address decoder to decode the address and determine which control register set will receive the data packet. In other words, although all buffer register sets receive the data packet, only one control register set receives the transferred data packet. The buffer register sets not loading the designated control register set are considered xe2x80x9cdon""t carexe2x80x9d sets. Overflow conditions can occur in the don""t care sets. The buffer register set loading the designated control register set (called an active buffer register set) is typically sized for its received data stream. Therefore, an overflow condition typically does not occur in the active buffer register set. In one embodiment, some buffer registers load dynamically adjustable control values and other buffer registers load static configuration control values.
A method of transfering data to an integrated circuit is also provided. The method includes assessing the length of a data packet to be transferred, wherein the data packet includes a first bit and a last bit. Bits representing an address for the data packet can be appended after the last bit of the data packet. The data packet and the appended bits can then be transferred to the integrated circuit. The appended bits can be decoded to identify the address. At this point, the data packet can be loaded into a control register set identified by the address. The data packet can include a plurality of data streams, wherein each data stream can be three to N bits in length, wherein N is an integer. The method can further include buffering the data packet.